KITSW Main page
Dept. of Electronics & Communications Engg.
KITS Warangal
Faculty group mail-id : ece@kitsw.ac.in
 
Faculty Profile
Address/Contact
Office : Staff Room No. 210, Block-I
Phone: 0870-254888(ext:212)
Mobile: 8790657081
E-mail : chpk@ece.kitsw.ac.in
 
Education
B.Tech., E.C.Engg, JNTU, Hyderabad. (2009).
M.Tech., VLSI System Design, JNTU, Hyderabad. (2011).
Ph.D.(Pursuing), Low Power VLSI, JNTU, Hyderabad.
Ch. Pavan kumar
Asst.prof
Electronics & Communication Engg..
 
ACADEMIC AFFILIATION

Details

FromTo

Name of the Organization

Assistant Professor

July, 2009

June, 2013

 

Vaagdevi Engineering College, Warangal.

Assistant Professor

June, 2013

Till Date

 

Kakatiya Institute of Technology & Science, Warangal.

RESEARCH INTERESTS
  • Low Power VLSI
  • Nanoscale Devices
  • Device Modelling
  • Device Channalization/Fabrication
PUBLICATIONS

Publications  in Refereed Journals

S.No

Details

1

Ch.Pavan Kumar, Dr.K.Sivani, “Implementation of Efficient Parallel Prefix Adders for Residue Number System” International Journal of Computing and Digital Systems, Int. J. Com. Dig. Sys. 4, No.4 (Oct-2015), ISSN (2210-142X), http://dx.doi.org/10.12785/ijcds/040409

2

Ch.Pavan Kumar, Dr.K.Sivani, “A Comparative Approach between Conventional Mosfet and Tunnel Field Effect Transistors (Tfets)”, International Journal Of Core Engineering & Management (IJCEM), Special issue ICCEMT-2015(Dec-15), page no.326-335, ISSN: 2348 9510

3

Ch. Pavan Kumar, Dr. K.Sivani, “Modeling of Tunnel Field Effect Transistor for Ultra-Low Power Applications” Lecture Notes in Networks and Systems, Springer publications, ISSN: 2367-3370

   
Publications in Refereed Conference Proceedings

S.No

Details

1

Ch.Pavan Kumar, Dr.K.Sivani, “Compact Modeling of Tunnel Field Effect Transistor for Ultra-Low Power Design Applications” 5th International Conference on Advancements in Engineering and Technology (ICAET-2017), March 24-25, 2017, Punjab, India. ISBN Number: 978-81-924893-2-2

2

M.devadas, CH.Pavankumar, M. Sanjay and P.srujan “A Novel approach for fault tolerant nano memory applications,” in Proc. Of international conference on nanoscience, engineering & advanced computing (ICNEAC-2011) narsapur, W.G.DIST, Andhra pradesh, 8-10 July, 2011   (ISBN:978-81-8465-683-1)

3

  1. Ch.Pavan Kumar, Dr K.Sivani, “A Tunnel Field Effect transistor is a substitute for ultra-low power applications” International Conference on Advances in Human Machine Interaction (IEEE HMI 2016), March 3-5, 2016  ISBN Number : 978-1-4673-8810-8, DOI: 10.1109/HMI.2016.7449164

4

  1. Ch.Pavan Kumar, Dr.K.Sivani, “Analyzing the impact of TFETs for ultra-low power design applications.” International Conference on Electrical, Electronics, and Optimization Techniques (IEEE-ICEEOT), March 3-5, 2016.

DOI: 10.1109/ICEEOT.2016.7754753

5

Ch. Sravan, CH.Pavankumar, Dr. K. Sivani “A novel approach for power-gating technique with Improved Efficient Charge Recovery Logic in proc. Of International Conference on Smart Electric Grid (IEEE ISEG), 2014  ,vol., no., pp.1,8, 19-20 Sept. 2014 doi: 10.1109/ISEG.2014.7005583

6

Ch. Sravan, CH.Pavankumar, Dr. K. Sivani “A Novel Approach for Power Reduction in Asynchronous circuits by using AFPT” in proc. of Eleventh International Conference on Wireless and Optical Communications Networks (IEEE WOCN), 2014, Vol. No., pp.1 - 7, 11-13 Sept. 2014, DOI: 10.1109/WOCN.2014.6923091.

7

B. Komuraiah, P. Indraja, Ch.Pavankumar, A. Srinivas, G. RaghothamReddy “Novel Algorithm for Image Enhancement” in proc. Of International Conference on Recent Advances in Communication, VLSI & Embedded Systems (ICRACVES’14) held during 19th – 20th December, 2014 at SR Engineering College, Warangal, and Telangana, India.

8

B. Komuraiah, P. Indraja,J. Jasmitharani, Ch.Pavankumar, G. RaghothamReddy “A Novel Algorithm for Image Enhancement using Biomedical Images” in proc. Of International Conference on Recent Advances in Communication, VLSI & Embedded Systems (ICRACVES’14) held during 19th – 20th December, 2014 at SR Engineering College, Warangal, and Telangana, India.

9

Ch. PavanKumar, G. Chandana, Dr. K. Sivani “Kogge-Stone and Knowles Adders for High Speed and Reduced Area” in proc. Of National Conference on Recent Advances in Communications & Electronics (RACE-2015) held during 27th -28th February, 2015 at Kamala Institute of Technology & Science, Singapur, Telangana, India

10

B. Komuraiah, Ch. Pavan Kumar, D. Swathi, K. Sharath Krishna, M. Harish “The New Algorithm for Sparse Recovery” in proc. Of  National Conference on Recent Advances in Communications & Electronics (RACE-2015) held during 27th -28th February, 2015 at Kamala Institute of Technology & Science, Singapur, Telangana, India

   
PROFESSIONAL AFFILIATION

S.No

Details

1

Member – Institute of Electrical and Electronics Engineers (IEEE - 92553627)

2

Member – Indian Society for Technical Education (ISTE- LM 74251)

COURSES TAUGHT

Undergraduate Level

     

Courses Taught

Currently Teaching

Course

Semester, Year, Branch

Course

Semester, Year, Branch

Microprocessor and interfacing

II Sem, III/IV, IT

Microprocessor and System Interfacing

II Sem, III/IV, IT

Microprocessor and Microcontrollers

II Sem, III/IV, ECE, EEE

 

Embedded Systems

II sem, III/IV, ECE

 

 

VLSI Design and Technology

II Sem, III/IV, ECE

 

 

Electromagnetic Waves and Transmission Lines

II Sem, III/IV, ECE

 

 

Digital Logic Design & Computer Architecture

II Sem, III/IV, ECE

 

 

Switching Theory and Logic Design

II Sem, III/IV, ECE

 

 

Computer Architecture

II Sem, III/IV, ECE

   

Digital Design

II Sem, III/IV, ECE

   

 

 

   
Post Graduate Level

 

   

Mixed Signal Design

II Sem, M.Tech. VLSI & ES

 

 

Workshops ATTENDED
S. No. Details of the participation (Faculty development/training activities/STTPs)

1

AICTE sponsored Staff Development Program on ‘’Advanced Embedded and Real Time Operating Systems’’ Dept. of ECE, Jayamukhi Institute of Technological Sciences, Narasampet, Warangal, Andhra Pradesh, during 18th June to 1st July 2012.

2

Train the trainer program on analog system design using ASLK starter trainer kit, Organized by CMR Institute of Technology from 23rd to 25th July, 2012, Bangalore

3

3rd Research Methodology Course Organized by Jawaharlal Nehru Technological University Hyderabad, Research and Development Cell ,from 16th to 21st December,2013 at JNTUH Campus.

4

INUP Familiarization Workshop on Nanofabrication Technologies Organized by IIT Bombay, Mumbai during May 26-28,2014

5

INUP Familiarization Workshop on Nanofabrication Technologies Organized by IIT Bombay, Mumbai during November 28-30, 2014.

6

INUP Familiarization Workshop on Nanofabrication Technologies Organized by IIT Bombay, Mumbai during May 27-29, 2015.

7

INUP Hands-on Training Workshop on MOSCAP at IIT Bombay during April 18-22, 2016.

8

INUP Hands-on Training Workshop on MEMs at IIT Bombay during March 20-24, 2017.

9

IITBombayX: FDP101x Foundation Program in ICT for Education from 03 August to 13th September, 2017.

   
AICTE SPONSORED SDP :

participated in the AICTE sponsored Staff Development Program on ‘’Advanced Embedded and Real Time Operating Systems’’ organized by the Dept. of ECE, Jayamukhi Institute of Technological Sciences, Narasampet, Warangal, Andhra Pradesh, during 18th June to 1st July 2012.

PAPERS PRESENTED IN CONFERENCES/SEMINARS/ WORKSHOPS/SYMPOSIA

S. No.

Title of the Paper presented

Title of Conference/ Seminar etc.

Organized by

BOOKS PUBLISHED

S.No

Details

1

  1. A novel approach for fault tolerant Nano Memory Applications ISBN: 978-3-659-89441-1.

2

  1. Analog Interface Implementation of Glucometer in CMOS Technology ISBN: 978-3-330-34298-9.
INVITED LECTURES IN CONFERENCE/SEMINAR

S. No.

Title of Lecture/ Academic Session

Title of Conference/ Seminar etc.

Organized by

 

 
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